1. Field of the Invention
The present invention relates to a semiconductor circuit device that needs less power consumption.
2. Description of the Prior Art
FIG. 16 is a configuration of a semiconductor circuit device that uses conventional CMOS (Complementary Metal Oxide Semiconductor) circuits. In order to simplify the explanation, it is assumed here that the semiconductor circuit device comprises CMOS inverter circuits arranged in 3 stages. In FIG. 16, reference numeral 101 denotes a CMOS inverter circuit composed of a P-type transistor P1 and an N-type transistor N1. 102 denotes a CMOS inverter circuit composed of a P-type transistor P2 and an N-type transistor N2. 103 denotes a CMOS inverter circuit composed of a P-type transistor P3 and an N-type transistor N3. C1, C2, and C3 denote capacitances such as interconnecting capacitance formed between the output node of each of the CMOS inverter circuits 101, 102, and 103 and the ground respectively. 104 denotes an input signal to the CMOS inverter circuit 101. 105 denotes an output signal from the CMOS inverter circuit 103.
Next, the operation of the semiconductor circuit will be explained.
When the input signal 104 is at "L" level, the capacitances C1 and C3 are charged up to the power supply potential Vdd by the P-type transistors P1 and P3 provided in the CMOS inverter circuits 101 and 103 respectively. The capacitance C2 is discharged up to the ground potential by the N-type transistor N2 provided in the CMOS inverter circuit 102. When the input signal 104 is changed from "L" level to "H" level, the capacitances C1 and C3 are discharged up to the ground potential by the N-type transistors N1 and N3 provided in the CMOS inverter circuits 101 and 103 respectively. The capacitance C2 is charged up to the power supply potential Vdd by the P-type transistor P2 provided in the CMOS inverter circuit 102. When the input signal 104 is changed from "H" level to "L" level, the capacitances C1, C2, and C3 are charged or discharged in the same way in the range a potential between the power supply potential Vdd and the ground potential.
Although CMOS inverter circuits are picked up for explanation here, other CMOS circuits such as CMOS NAND and CMOS NOR circuits, as well as a BiCMOS circuit, which is a combination of CMOS and bipolar circuits, may be used to repeat charging and discharging between power supply potential and ground potential to transmit signals as explained above.
Since the conventional semiconductor circuit device is constructed as described above, the electric charge charged up to the power supply potential Vdd is discharged completely each time a signal is changed, and accordingly the conventional semiconductor circuit device has a problem that the circuit needs much power consumption.
FIG. 17 is a configuration of the concept on how to reuse an electric charge, disclosed in JP-A No. Hei 7-141877. In FIG. 17, C0, C1, and C2 denote capacitances. SC1 and SC2 denote switches for charging the capacitances C1 and C2 up to the power supply potential Vdd. SD1 and SD2 denote switches for discharging electric charges sent from the capacitances C1 and C2. ST1 and ST2 denote switches for connecting the capacitance C1 to the capacitance C0 and the capacitance C2 to the capacitance C0. t1 to t9 denote times for turning on/off switches sequentially.
When the switches SC1, ST1, and SD1 are turned on/off at the times t1, t2, and t3 sequentially, the electric charge charged in C1 up to the power supply potential Vdd is transferred to C0 and accordingly, C1 is discharged. Then, when the switches ST2 and SC2 are turned on/off at the times t4 and t5 sequentially, the electric charge in C0 is transferred to C2, and C2 is charged up to the power supply potential Vdd. When the switches ST2 and SD2 are turned on/off at t6 and t7 sequentially, the electric charge in C2 is transferred to C0, and accordingly, C2 is discharged. Then, when the switches ST1 and SC1 are turned on/off at t8 and t9 sequentially, the electric charge in C0 is transferred to C1, and accordingly, C1 is charged up to the power supply potential Vdd.
As explained above, the potential of the capacitance C1, when the logic is changed from "H" level to "L" level, and to "H" level again, allows the electric charge to be reused by transferring electric charges. When the logic is changed from "H" level to "L" level, and to "L" level, however, the switch SD1 is turned on/off at t9 instead of the switch SC1. At this time, the C1 is discharged completely, so the electric charge cannot be reused depending on the logic change. The conventional semiconductor circuit device has the above-described problem.